The present invention generally relates to semiconductor devices and fabrication process thereof, and especially to the fabrication process of a semiconductor device in which a layer of low-resistance nickel silicide, particularly a nickel silicide layer of the NiSi composition is formed on the diffusion region or gate electrode on a semiconductor substrate.
In the art of MOS semiconductor integrated circuit devices, steady progress is being made with regard to improvement of integration density and miniaturization of device size for the purpose of achieving higher operational speed, further diversity of functions, larger memory capacity, further decrease of electric power consumption, or the like.
Today, there is already realized a semiconductor device having a gate length of 100 nm or less, while with such ultra-miniaturized semiconductor devices, there arise various problems in relation to decrease of the gate length. Thus, innovation of the conventional art is inevitable.
Conventionally, a vertical interconnection structure such as contact structure has been used extensively in semiconductor devices formed on a silicon substrate for electrically interconnecting a diffusion region formed in the silicon substrate with an interconnection pattern.
With such a contact structure, an electric interconnection is made to the surface of the diffusion region by way of a contact plug. Thereby, in order to reduce the contact resistance, it is practiced in the art to form a low-resistance silicide layer on the surface of the diffusion region to which the contact plug makes a contact.
Conventionally, such a silicide layer is formed by a so-called salicide process in which a metal film is deposited on a silicon surface, followed by a thermal annealing process such that there is caused a reaction between the metal film and the silicon surface. After the thermal annealing process, the metal film remaining unreacted is removed by a selective wet etching process.
In the case of ultra-miniaturized semiconductor devices of these days called 65 nm-node generation devices or newer and characterized by the gate length of 35 nm or less, it is preferable to suppress the junction depth of the source/drain diffusion regions to be 100 nm or less in view of the need of suppressing short channel effect.
In relation to this, there is an increasing need of using nickel silicide, which can be formed with thermal annealing process at the temperature of 400° C. or less, in the salicide process, such that the distribution profile of the impurity elements constituting the shallow junction is not modified with the thermal annealing process. In addition, nickel silicide can be formed also on a SiGe mixed crystal region with reliability. Thus, nickel silicide is an indispensable material in the ultra-fast semiconductor devices that achieve improvement of operational speed by way of stressing.